A. Field Of The Invention
This invention relates generally to image processing techniques and more particularly, to apparatus and techniques for optimizing the resolution of scanned imaging systems. Even more particularly, the invention relates to an improved apparatus and novel method of clocking a time delay and integrate charge-coupled device to extend its operational coverage (e.g., in an airborne reconnaissance application, at higher velocity to altitude ratios) by increasing the rate of charge motion through the device in synchronism with an increased image scan speed with only minimal losses of image resolution.
B. Description Of Related Art
Time delay and integrate charge-coupled devices are solid state imaging devices that use a flow of charge through an array to image a scene. Background information on charge-coupled devices can be found in Streetman, Solid State Electronic Devices, Prentice-Hall pp. 355-361 (1980), and in Schroder, Modular Series on Solid State Devices-Advanced MOS Devices, Addison-Wesley Pub. Co., ch. 3, 4 (1987). An additional reference discussing charge transfer and charge-coupled devices is C. Sequin and M. Tompsett, Charge Transfer Devices, Bell Telephone Laboratories, Academic Press (1975). The time delay and integrate mode of operation of a charge-coupled device is a well-known technique for increasing the sensitivity of a line scan imaging array.
A time delay and integrate charge-coupled device may, as an example, have sixty-four rows (or more) of charge integration with a horizontal resolution of perhaps 2,048 pixel elements, arranged in a linear array. By synchronizing the relative motion of the image scene down the array with a clock frequency in the vertical (time delay and integrate) direction, the charge containing scene information is summed over the number of available time delay and integrate rows across the 2,048 columns. Time delay and integrate mode of operation thus effectively increases the total array exposure time to the image by a factor of 64, compared to a typical line scan sensor, without sacrificing the resolution in the scan direction or the scanning speed.
The increased sensitivity gained in time delay and integrate mode makes the charge-coupled device a particularly useful imaging device in aerial reconnaissance photography, particularly in low light conditions. For details on how such a charge-coupled device may be designed and built, see A. Lareau & C. Chandler, Advanced CCD Reconnaissance Detector, Vol. 694, Proceedings of SPIE--The International Society for Optical Engineering (1987).
In operation, the image from the scene is scanned by a mirror to impinge on the front row of the array. The electrical signal (a charge packet) containing scene information will be collected in the potential wells of the front row during an integration period which corresponds to one line time. One line time equals 1/vertical clock frequency. The charge packet is then shifted vertically to the next sequential row after one line time. As the scene is allowed to be imaged on the subsequent row, the charge packets created are summed with those of the previous row. This process is repeated over the time delay and integrate rows, finally resulting in a line (row) of 2,048 elements that have integrated 64 line times in our example. The information is then transferred in parallel via a transfer pulse to a horizontal output shift register, to be clocked out serially within one line time. Since the subsequent scene follows only one row behind, the next line scan is read out only one line time later. In this way, the charge-coupled device puts out one line of image every line time continuously.
To assist in understanding how a time delay and integrate charge-coupled device uses the flow of charge packets through an array in synchronism with a scanned image that impinges on the array, the reader is directed to FIG. 1 which is an illustration of how charge packets containing scene information are moved through a prior art time delay and integrate charge-coupled device in synchronism with a scanned image. The imaging array of an exemplary prior art time delay and integrate charge-coupled device 10 is shown as having 64 rows (e.g., exemplary rows RW1, RW2, and RW62-64) of 2,048 columns (e.g., exemplary columns C1-C4 and C2,045-C2,048). The scan line 12 of an image impinges on the array in row RW64. Electrical signals (charge packets) containing pixel information representing scan line 12 will be collected in the potential wells of row RW64 during an integration period of one line time. The charge packet is then shifted vertically to the next row, RW63. As the scan line is imaged on row RW63, the charge packets created are summed with those from row RW64, while a new scan line of the image is now scanned on row RW64. This process is repeated over the 64 rows resulting, in row RW1, a row of 2,048 elements that have integrated for 64 line times. The pixel information in row RW1 is then transferred in parallel via a transfer pulse to a row readout device, such as an output multiplexer 14, and is clocked out serially within 1 line time (i.e., one row readout time period). Since the subsequent scan line of the scene follows only one row behind, the next line scan is read out, containing new pixel information, only one line time later. Thus, the array reads out scene scan line information continuously one line at a time.
FIG. 2 is a diagram of the representative prior art array of FIG. 1, but showing the relationship between the array 10 and the external clock inputs that control the charge motion. FIG. 2 shows a 64-stage shift register 16 having stages 1-64 (e.g., exemplary stages SR1-SR64 and SR62-SR64) and a 64-stage corresponding clock driver 18. The output of each stage of shift register 16 drives the corresponding stages of the clock driver 18 as shown by the arrows. The 64 stage clock driver 18 drives its corresponding array row (or phase) as shown. It is conventional to show the internally generated clocks .phi..sub.1 -.phi..sub.64 for the rows on conductors C.phi..sub.1, C.phi..sub.2, through C.phi..sub.64.
The external interface to this circuitry includes 3 clock signals, shown in FIG. 2 as an initiating or trigger clock signal R.sub.IN, and ripple clock signals R.sub.1 and R.sub.2, that are conducted over conductors CR.sub.in, CR.sub.1 and CR.sub.2, respectively. Signal R.sub.IN injects a zero "0" pulse into the input end 20 of shift register 16. Signals R.sub.1 and R.sub.2 shift the injected "0" stage by stage through the shift register, with each cycle of R.sub.1 and R.sub.2 shifting the "0" one stage.
A cycle of operation of the charge couple device (called "burst ripple" clocking) consists of injecting the trigger clock Rin into the shift register 16 and shifting, one row at a time, the charge packets down the rows of the array 16. If the cycle is repeated once each line time, the charge packets travel one line height per line readout time over the entire array. This is the line rate at which the target image scan must be synchronized for time delay and integrate operation to avoid image smear, or, in other words, to achieve full image resolution in the scan direction.
Referring now to FIG. 3a, the 64 phase clocking known in the art is illustrated. The signal R.sub.IN, at time t=0, is injected into the input end of the shift register 16, and the R.sub.1 and R.sub.2 signals shift the "0" pulse stage by stage through the shift register 16. This shifting of the "0" pulse through the shift register causes the internal clocking of the 64-stage clock driver 18 to generate the clocking shown. First, clock .phi..sub.1 (for row RW1) outputs a "0" pulse, then clock .phi..sub.2, etc., up to clock .phi..sub.64. The time it takes to "ripple" through the 64-stage clock driver 18 is 1 line time. In one row readout time period, all the charge packets in the rows of the array are shifted by one row. FIG. 3a shows 1 cycle of 64 phase clocking.
FIG. 3b shows the motion and position of charge packets in one column of the array 10, arbitrarily selected to be column Ci, at various separated points in time during one line time (i.e., time t=0 to time t=LT). The points in time T1--T7 and T127 shown in FIG. 3a are repeated in FIG. 3b to show the times when the motion of the charge packets occurs. At time T1, while .phi..sub.1 is in a "0" state, charge packet 22 in column Ci is shifted from row RW1 to output multiplexer 14 as shown by arrow 24. At time T2 after the shifting is completed and .phi..sub.1 has returned to the "1" state, charge packet 22 is absent from row RW1. At time T3, while .phi..sub.2 is in a "0" state, charge packet 26 in column Ci is shifted from row RW2 to row RW1 as shown by arrow 28. At time T4, after the shifting is completed and .phi..sub.2 has returned to its "1" state, charge packet 26 is absent from RW2. At time T5, while .phi..sub.3 is in a "0" state, charge packet 30 in column Ci is shifted from row RW3 to RW2 as shown by arrow 32. At time T6, after the shifting is completed and .phi..sub.3 has returned to its "1" state, charge packet 30 is absent from row RW3. At time T7, while .phi..sub.4 is in a "0" state, charge packet 34 in column Ci is shifted from row RW4 to row RW3 as shown by arrow 36. At time T127, while .phi..sub.64 is in a "0" state, charge packet 38 in column Ci is shifted from row RW64 to row RW63 as shown by arrow 40.
FIG. 3c shows four "snap-shots" of the whole array 10 at t=T1, t=T3, t=T5 and t=T127 given the clocking of FIG. 3b. Each "snap-shot" of the array shows the movement of charge from one row to an adjacent row. After 64 line times, the scene in row RW64 at t=0 will have been shifted down and out of the array. Note that by clocking in the above known manner, all charge packets remain separated. The scan speed is synchronized with the rate of charge motion which is approximately one line height in one line readout time.
Any charge-coupled device has a maximum line or row readout rate constrained by the pixel output rate. The readout rate is the reciprocal of the row readout time period and generally is expressed in rows read out per second. As a result, any charge-coupled device is constrained to a maximum scan rate with full resolution. Scanning faster (i.e., having the row scan rate exceed the row readout rate) without increasing the rate of charge motion only smears the image. When the airplane velocity to height ratio exceeds the operational limits of the charge-coupled device, image resolution decreases rapidly as prior art clocking is performed, thus constraining the airplane to relatively low velocity to height scenarios.
In an airborne reconnaissance application, as the aircraft velocity to height ratio increases, e.g., the airplane's velocity increases or it flies at a lower altitude, the airplane passes over more ground in less time. At some point, the limiting maximum scan rate causes the device to miss a portion of the ground scene due to the high velocity to height ratio exceeding the limit for full operational coverage. To remedy the situation, one could try to double the scan rate to double the coverage. However, if one keeps the same line rate and "burst ripple" clocking while operating in a 64 row time delay and integrate mode, the image would be smeared to 1/32 of full resolution. This drastic reduction in resolution is the result of non-synchronous scan speed versus charge motion. Note that if one were utilizing only the first time delay integrate row, in a best case scenario, the resolution at double the scan rate would be reduced by one half.
It is thus a principal object of the present invention to increase and extend the operational coverage of imaging systems while at the same time optimizing image resolution.
It is another object of the invention to enable imaging systems to be used in velocity and height regimes that are extended beyond the typical operational coverage of such devices.
Yet another object of the invention to enable an airplane carrying a time delay and integrate charge-coupled imaging device to fly faster and at lower altitudes than before, with optimal resolution capability.
Still another object of the invention is to enable an airplane carrying a time delay and integrate charge-coupled imaging device in a military scenario to decrease the risk of enemy detection and hostile fire while still creating a image of acceptable resolution.